The present invention relates to a memory-mounting integrated circuit and a test method of the memory region of a memory-mounting integrated circuit onto which a memory is mounted.
Capacity of a memory to be mounted on an integrated circuit is becoming massive every year and importance of a test method on such a memory with massive capacity is becoming intensive every day. As a method to test such a memory for a memory-mounting integrated circuit, there is a method in which a memory is separated from a logic circuit so as to test the memory alone with a tester from outside.
However, when such a method is going to go with a test on the logic section using a logic tester at the same time, a test vector gets fairly long and thus the tester will need a lot of vector memories. In addition, when a memory tester is independently used apart from the test on a logic circuit, costs for a tester to be used will be additionally incurred. In addition, not only that but also rapid testing will generally become impossible since it is necessary for a separated memory terminals to be drawn out to outside an integrated circuit for measurement.
Moreover, a memory of multi-bits more likely gives rise to a shortage of the number of input-output terminals securable for a test.
As a test method to avoid such a disadvantage, there is a BIST (Built in Self Test) method. This method gives rise to an advantage that a test vector generating circuit to test a memory on an integrated circuit and a quality judging circuit are mounted on an integrated circuit so that an enlarged test vector or a special memory tester and an input-output terminal for testing becomes no longer necessary and the memory can be tested under a rapid operation equivalent to an actual working conditions.
Thus, simplifying the testing is a major object of the BIST, but in general test results are limited to quality judging only, and in the case where an integrated circuit is defective, it is configured that it is impossible to know contents of defectiveness such as what kind of the defect it is in fact or in which portion of a memory of an integrated circuit the defective bit is.
Therefore, there is a disadvantage that a normally known BIST test method cannot be utilized for redundancy relief judgment to improve the yield factor of a memory. In addition, when problems on manufacturing of integrated circuits such as decrease in the yield factor arise, such information of the defective bit cannot be efficiently used for analyses on the above described problems, etc., preventing understanding on the cause with regard to manufacturing, and thus it is not reflection of a production line.
Among these problems, a technology using BIST for redundancy relief judgment is exemplified by the invention described in Japanese Patent Laid-Open No. HEI 9-251796 (251796/1997). However, the object of the technology disclosed in that publication is purely redundancy relief, and is limited by having an object to monitor from outside only the information on possibility of redundancy relief or on which line to be replaced so as to make relief available.
In addition, Japanese Patent Laid-Open No. HEI 10-302499 (302499/1998) also describes an invention similar to the above described one, and as a principle for such an invention, the information necessary for redundancy relief according to defects is piled temporarily in a separate memory called fail memory, and is outputted to the outside logic tester at completion of the test so that the test results in the logic section as well as quality on the integrated circuit are judged and the data necessary for redundancy relief is arranged to be prepared. This principle gives rise to a limit on the information available for notice outside in accordance with sizes of mountable fail memories. Accordingly, the information available therefrom only cannot provide with information such as the quantity of defective bits or information on sections thereof as well as address dependency of the defective bits or contents on defects, etc., necessary to solve essential problems when they are given rise to in processes or circuits.
The object of the present invention is to provide such a memory-mounting integrated circuit as well as a memory test method that can reduce costs to incur for a tester, regulate the number of the input-output terminals for testing, and nevertheless can monitor from outside all the contents of defects in principle.
The invention of a memory-mounting integrated circuit according to claim 1 is a memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, in which the above described BIST circuit includes, data storing means for storing the data in a normal memory, comparing means for comparing a memory test result signal from the above described memory with data from the above described data storing means to output a first comparing signal, control means for controlling to implement outputting outward from the first comparing signal outputted by the above described comparing means, and output means for outputting defective data outward by the above described control means.
The invention of a memory-mounting integrated circuit according to claim 2 is a memory-mounting integrated circuit, according to claim 1, wherein said comparing signal is a defective detecting signal.
The invention of a memory-mounting integrated circuit according to claim 3 A memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, wherein said BIST circuit comprises data storing means for storing data in a normal memory, comparing means for comparing a memory test result signal from said memory with the data from said data storing means for outputting a first comparing signal, control means for controlling to implement outputting outward from the first comparing signal outputted by said comparing means, output means for outputting defective data outward by said control means, address generating means for operating said memory and data generating means for testing the data, wherein said control means control said address generating means and said data generating means.
The invention of a memory-mounting integrated circuit according to claim 4 comprises, a memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, wherein said BIST circuit comprises: data storing means for storing data in a normal memory, comparing means for comparing a memory test result signal from said memory with the data from said data storing means for outputting a first comparing signal, control means for controlling to implement outputting outward from the first comparing signal outputted by said comparing means, output means for outputting defective data outward by said control means, and judging means for comparing said memory test result signal with data from said data storing means so as to determine ending of a test or continuation of the test.
The invention of a memory-mounting integrated circuit according to claim 5 comprises, a memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, wherein said BIST circuit comprises: data storing means for storing data in a normal memory, comparing means for comparing a memory test result signal from said memory with the data from said data storing means for outputting a first comparing signal, control means for controlling to implement outputting outward from the first comparing signal outputted by said comparing means, output means for outputting defective data outward by said control means, address generating means for operating said memory, data generating means for testing the data wherein said control means control said address generating means and said data generating means, and judging means for comparing said memory test result signal with data from said data storing means so as to determine ending of a test or continuation of the test.
The invention of the test method of a memory-mounting integrated circuit according to test claim 6 is a method of testing a memory region of the memory-mounting integrated circuit on which a BIST circuit and a memory are mounted, wherein said test method is featured by outputting outward only data on addresses where defects are found and addresses.
The invention of the test method of a memory-mounting integrated circuit according to test claim 7 is a method of a testing memory region method of a memory-mounting integrated circuit to test a memory region of the memory-mounting integrated circuit on which a BIST circuit and a memory are mounted, wherein said test method is featured by outputting outward only data on addresses where defects are found and addresses, said memory region is halted in the case where only the data on addresses in which said defects are found and the addresses are outputted outward, and the testing on said memory region is resumed when said outputting comes to an end.
The invention of the test method of a memory-mounting integrated circuit according to test claim 8 is a method of a testing of the memory-mounting integrated circuit on which a BIST circuit and a memory are mounted, wherein said test method is featured by outputting outward only data on addresses where defects are found and addresses, and end of the testing or continuation of the testing is determined by the data on addresses where the above described defects are found and the addresses.
The invention of the test method of a memory-mounting integrated circuit according to test claim 9 is a method of the memory-mounting integrated circuit on which a BIST circuit and a memory are mounted, wherein said test method is outputting outward only data on addresses where defects are found and addresses, said memory region is halted in the case where only the data on addresses in which said defects are found and the addresses are outputted outward, the testing on said memory region is resumed when said outputting comes to an end and end of the testing or continuation of the testing is determined by the data on addresses where the above described defects are found and the addresses.